On 02/12/15 18:44, Rob Herring wrote:
On Wed, Dec 2, 2015 at 10:49 AM, Martyn Welch
<martyn.welch@xxxxxxxxxxxxxxx> wrote:
On 02/12/15 15:15, Rob Herring wrote:
On Tue, Dec 01, 2015 at 07:12:49PM +0000, Martyn Welch wrote:
This patch adds documentation for the chromeos-firmware binding.
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Pawel Moll <pawel.moll@xxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: Ian Campbell <ijc+devicetree@xxxxxxxxxxxxxx>
Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Signed-off-by: Martyn Welch <martyn.welch@xxxxxxxxxxxxxxx>
---
.../devicetree/bindings/misc/chromeos-firmware.txt | 27
++++++++++++++++++++++
bindings/firmware/ please.
OK.
1 file changed, 27 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/chromeos-firmware.txt
diff --git a/Documentation/devicetree/bindings/misc/chromeos-firmware.txt
b/Documentation/devicetree/bindings/misc/chromeos-firmware.txt
new file mode 100644
index 0000000..8240611
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/chromeos-firmware.txt
@@ -0,0 +1,27 @@
+Device-Tree bindings for chromeos-firmware.c.
Perhaps a bit more description what this is.
What aspect of this is firmware? How does this relate to the EC?
With respect to write-protect, this line is the write protection for the
flash which holds the bootloader.
What is driving the write-protect? Are trying to assign ownership of
the SOC GPIOs to the bootloader/firmware? If so, I think this is all
wrong.
The lines are typically driven by a debugging board plugged into a
socket on the Chromebooks motherboard, not by the device it's self. The
driver exposes a read-only interface to these signals.
Martyn
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