On 11/01/2013 02:06 AM, Hiroshi Doyu wrote:
> On Thu, 31 Oct 2013 18:46:06 +0100
> Mark Rutland <mark.rutland@xxxxxxx> wrote:
>
>> On Thu, Oct 31, 2013 at 08:19:42AM +0000, Hiroshi Doyu wrote:
>>> Stephen Warren <swarren@xxxxxxxxxxxxx> wrote @ Wed, 30 Oct 2013 23:48:38 +0100:
>>>
>>>> On 10/18/2013 04:26 AM, Hiroshi Doyu wrote:
>>>>> Create a header file to define the swgroup IDs used by the IOMMU(SMMU)
>>>>> binding. "swgroups" is a group of H/W clients which Tegra SoCs
>>>>> support. This unique ID can be used to calculate MC_SMMU_<swgroup
>>>>> name>_ASID_0 register offset and MC_<swgroup name>_HOTRESET_*_0
>>>>> register bit. This will allow the same header to be used by both
>>>>> device tree files, and drivers implementing this binding, which
>>>>> guarantees that the two stay in sync. This also makes device trees
>>>>> more readable by using names instead of magic numbers.
>>>>
>>>>> diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h
>>>>
>>>>> +#define TEGRA_SWGROUP_PPCS2 32 /* 0xab0 */
>>>>> +
>>>>> +#define TEGRA_SWGROUP_BIT(x) (1ULL << TEGRA_SWGROUP_##x)
>>>>
>>>> Isn't the DT match all 32-bit, such that the ULL suffix does nothing,
>>>
>>> For the future Tegra SoC, the number of HWA grows a bit more, and it's
>>> supposed that "64" would be enough.
>>
>> Does DTC accept 64-bit values as-is? I recall DTC shouting at me in the past,
>> and having to split values across two u32 cells (i.e. <0xffffffff 0xffffffff>
>> rather than <0xffffffffffffffff>).
>
> TEGRA_SWGROUP_BIT was only used in driver code since DT couldn't handle OR("|").
>
> Stephen pointed out the latest DT can do. So this macro should be
> revised to be used in DTS as well.
One note: If there was no intention to use the #defines in
<dt-bindings/memory/tegra-swgroup.h> in the DT before, that header
shouldn't have been in the <dt-bindings> directory. That said, given the
bug is really that the DT wasn't using the header but should have been,
fixing the DT is the right way to go.
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