Re: [PATCH 2/3] clk: add Dove PLL divider support for GPU, VMeta and AXI clocks

[Andrew Lunn <andrew@xxxxxxx>]

Hi Russell

> +static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate,
> +			     unsigned long parent_rate, bool set)
> +{
> +	unsigned int divider, max;
> +
> +	divider = DIV_ROUND_CLOSEST(parent_rate, rate);
> +
> +	if (dc->divider_table) {
> +		unsigned int i;
> +
> +		for (i = 0; dc->divider_table[i]; i++)
> +			if (divider == dc->divider_table[i]) {
> +				divider = i;
> +				break;
> +			}
> +
> +		if (dc->divider_table[i])
> +			return -EINVAL;

Is this condition correct? If we have reached the 0 at the end of the
table, -EINVAL makes sense. But that would need a !

       Andrew
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