From: Carlo Caione <carlo@xxxxxxxxxxxx>
This patch extends the L2 cache controller node for Amlogic Meson8b
SoCs with some missing parameters.
Signed-off-by: Carlo Caione <carlo@xxxxxxxxxxxx>
---
arch/arm/boot/dts/meson8b.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 8bad557..745f0f9 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -93,6 +93,9 @@
L2: l2-cache-controller@c4200000 {
compatible = "arm,pl310-cache";
reg = <0xc4200000 0x1000>;
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x100000 0xc0000000>;
cache-unified;
cache-level = <2>;
};
--
2.5.0
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