On 11-11-15 07:50, R, Vignesh wrote:
Hi Brain,
On 11/11/2015 4:53 AM, Brian Norris wrote:
Hi Vignesh,
...
Also, this API doesn't actually have anything to do with memory mapping.
It has to do with the de facto standard flash protocol. So I don't think
mmap belongs in the name; it should be something about flash. (I know of
at least one other controller that could probably use this API, excpet
it doesn't use memory mapping to accomplish the accelerated flash read.)
The Zynq has a similar way of accessing QSPI flash through a memory map. The
memory window is only 16MB, so some form of paging would be needed.
It's why I have been following this thread with great interest, since the QSPI
performance on the Zynq is way below what it could potentially be.
As far as TI QSPI controller is concerned, the accelerated read happens
via mmap port whereby a predefined memory address space of SoC is
exposed as QSPI mmap region. This region can be accessed like normal
RAM(via memcpy()) and the QSPI controller interface takes care of
fetching data from flash on SPI bus automatically hence, I named it as
above. But, I have no hard feelings if it needs to be generalized to
spi_mtd_read() or something else.
I know that on the Zynq, you can even let the DMA controller access the QSPI
flash via this memory mapping. The QSPI controller itself doesn't support any
DMA at all.
If something similar applies to the TI platform (most of the TI procs have
nice DMA controllers) one could go one step further and implement a generic
DMA-through-mmap access to QSPI flash.
Mike.
Kind regards,
Mike Looijmans
System Expert
TOPIC Embedded Products
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