On Thu, 2015-11-12 at 10:42 +0000, Liviu Dudau wrote: > > This is on-chip RAM or nornal system RAM? We already have bindings > for > > both. > > Juno has a set of TLX (ThinLinks) connectors on the board where an > FPGA can be attached. On r1 > the code running on FPGA can even participate as an AXI master with > full coherency. The FPGA > has local memory that we want to share with the HDLCD to be used as a > framebuffer. The HDLCD on the Juno chip or one implemented in the FPGA? I assume you mean the latter but just wanted to check. -- Tixy -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
