On 11/2/2015 3:55 PM, Arnd Bergmann wrote:
Are you using message signaled interrupts then?
Typically MSI guarantees
ordering against DMA, but level or edge triggered interrupts by definition
cannot (at least on PCI, but most other buses are the same way), because
the DMA master has no insight into when a DMA is actually complete.
If you use MSI, please add a comment to the readl_relaxed() that it
is safe because of that, otherwise the next person who tries to debug
a problem with your driver has to look into this.
No, using regular GIC SPI interrupts at this moment. I know that HW
doesn't use any of the typical AHB/AXI ARM buses.
I'm familiar with how PCI endpoints works. While the first read in a
typical PCI endpoint ISR flushes all outstanding requests traditionally
to the destination, this concept does not apply here for this HW.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
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