From: J Keerthy <j-keerthy@xxxxxx>
The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: J Keerthy <j-keerthy@xxxxxx>
Signed-off-by: Tero Kristo <t-kristo@xxxxxx>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index ba43e7d..1226921 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,11 +1165,19 @@ cm_core: cm_core@4a008000 {
ti,invert-autoidle-bit;
};
+ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+ #clock-cells = <0>;
+ reg = <0x021c 0x4>;
+ ti,bit-shift = <7>;
+ };
+
apll_pcie_ck: apll_pcie_ck {
#clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
- reg = <0x0200>, <0x0204>, <0x0208>, <0x020c>;
+ compatible = "ti,dra7-apll-clock";
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x021c>, <0x0220>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
--
1.7.9.5
--
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