From: "Ivan T. Ivanov" <iivanov@xxxxxxxxxx>
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov <iivanov@xxxxxxxxxx>
Acked-by: Stephen Warren <swarren@xxxxxxxxxx>
---
.../devicetree/bindings/usb/msm-ssusb.txt | 105 ++++++++++++++++++++
1 file changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
new file mode 100644
index 0000000..a71bf00
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -0,0 +1,105 @@
+MSM SuperSpeed DWC3 USB SoC controller
+
+
+MSM DW Highspeed USB PHY
+========================
+Required properities:
+- compatible: should contain "qcom,dw-hsphy";
+- reg: offset and length of the register set in the memory map
+- clocks: A list of phandle + clock-specifier pairs for the
+ clocks listed in clock-names
+- clock-names: Should contain the following:
+ "xo" External reference clock
+ "sleep_a" Sleep clock, used when USB3 core goes into low
+ power mode (U3).
+- v1p8-supply: phandle to the regulator for the 1.8v supply to HSPHY.
+- v3p3-supply: phandle to the regulator for the 3.3v supply to HSPHY.
+- vbus-supply: phandle to the regulator for the vbus supply for host
+ mode.
+- vddcx-supply: phandle to the regulator for the vdd supply for HSPHY
+ digital circuit operation.
+
+MSM DW Superspeed USB PHY
+=========================
+Required properities:
+- compatible: should contain "qcom,dw-ssphy";
+- reg: offset and length of the register set in the memory map
+- clocks: A list of phandle + clock-specifier pairs for the
+ clocks listed in clock-names
+- clock-names: Should contain the following:
+ "xo" External reference clock
+ "ref" Reference clock - used in host mode.
+- v1p8-supply: phandle to the regulator for the 1.8v supply to HSPHY.
+- vddcx-supply: phandle to the regulator for the vdd supply for HSPHY
+ digital circuit operation.
+
+MSM DWC3 controller wrapper
+===========================
+Required properties:
+- compatible: should contain "qcom,dwc3"
+- reg: offset and length of the TCSR register for routing USB
+ signals to either picoPHY0 or picoPHY1.
+- clocks: A list of phandle + clock-specifier pairs for the
+ clocks listed in clock-names
+- clock-names: Should contain the following:
+ "core" Master/Core clock, have to be >= 125 MHz for SS
+ operation and >= 60MHz for HS operation
+ "iface" System bus AXI clock
+ "sleep" Sleep clock, used when USB3 core goes into low
+ power mode (U3).
+ "utmi" Generated by HSPHY. Used to clock the low power
+ parts of thr HS Link layer.
+Optional regulator:
+- gdsc-supply: phandle to the regulator from globally distributed
+ switch controller
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Example device nodes:
+
+ dw_hsphy: phy@f92f8800 {
+ compatible = "qcom,dw-hsphy";
+ reg = <0xf92f8800 0x30>;
+
+ clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
+ clock-names = "xo", "sleep_a";
+
+ vbus-supply = <&supply>;
+ vddcx-supply = <&supply>;
+ v1p8-supply = <&supply>;
+ v3p3-supply = <&supply>;
+ };
+
+ dw_ssphy: phy@f92f8830 {
+ compatible = "qcom,dw-ssphy";
+ reg = <0xf92f8830 0x30>;
+
+ clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
+ clock-names = "xo", "ref";
+
+ vddcx-supply = <&supply>;
+ v1p8-supply = <&supply>;
+ };
+
+ usb@fd4ab000 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xfd4ab000 0x4>;
+
+ clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>,
+ <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
+ clock-names = "core", "iface", "sleep", "utmi";
+
+ gdsc-supply = <&supply>;
+
+ ranges;
+ dwc3@f9200000 {
+ compatible = "snps,dwc3";
+ reg = <0xf9200000 0xcd00>;
+ interrupts = <0 131>;
+ usb-phy = <&dw_hsphy>, <&dw_ssphy>;
+ tx-fifo-resize;
+ };
+ };
--
1.7.9.5
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