The SIC is cascaded off the PIC, so specify this in the device tree.
Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
---
arch/arm/boot/dts/integratorcp.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index ff1aea0..f0ab05f 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -48,8 +48,11 @@
valid-mask = <0x00000007>;
};
+ /* The SIC is cascaded off IRQ 26 on the PIC */
sic: sic@ca000000 {
compatible = "arm,versatile-fpga-irq";
+ interrupt-parent = <&pic>;
+ interrupts = <26>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xca000000 0x100>;
--
1.8.3.1
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