On Wed, Oct 2, 2013 at 8:49 PM, Russell King - ARM Linux <linux@xxxxxxxxxxxxxxxx> wrote: > This apparantly is done by configuring the PLL on the IMX6 to 25MHz and > getting it to output it on this pin, and that is done in the freescale > BSP by this pin control setting: > > MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT > > Now, if you look up that in the 4.1.0 BSP: > > #define MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \ > IOMUX_PAD(0x05E4, 0x0214, 0x12, 0x080C, 0, NO_PAD_CTRL) > > and that says to write 0x12 to 0x20e0000 + 0x214 - the > IOMUXC_SW_MUX_CTL_PAD_GPIO16 register. This name clearly implies that > the IMX6 is _outputting_ the reference clock. The register values here > selects MUX_MODE 2 (ENET_REF_CLK) _with_ SION set. There is no > configuration in this BSP for GPIO 16 in mux mode 2 without SION set. SION bit is set for this pad in mainline as well: MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 (bit 30 is set, which indicates SION). -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
