On Thursday, 12 September, 2013 at 2:35 PM, Zhu Richard-R65037 wrote: > Hi Sean Cross: > See my comments marked by Richard. > [Richard] It's better to arrange the memory layout like the following one, then the 8MB mem-space can be allocated. > ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ > 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ > 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ Thank you. I'll update the DT file with this new ranges. > +/* Read from the 16-bt PCIe PHY control registers (not memory-mapped) > [Richard]16-bit? Oops. Sloppy. Good catch. > [Richard] As we know that lvds1 can be configured as input or output. > How do you present them by the name of "lvds1_gate"? This particular clock maps to LVDS1/2_oben and effectively acts as a gate. Only bits 10 and 11 are exposed in clk-imx6q.c. > + mdelay(100); > [Richard] mdelay(100) is too long, please use usleep_range(xxx,xxx You're right, and 100 is entirely too long to begin with. I'll cut this value down and use a range, as suggested. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
