vf610-twr has two s25fl128s SPI NOR flashs connected to QuadSpi0.
Add support for them.
Note: we enable the DDR Quad read for the two NOR flashs which runs
in 66MHz.
Signed-off-by: Huang Shijie <b32955@xxxxxxxxxxxxx>
---
arch/arm/boot/dts/vf610-twr.dts | 36 ++++++++++++++++++++++++++++++++++++
1 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 1a58678..063e94d 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -62,3 +62,39 @@
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
+
+&qspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0_1>;
+ num-cs = <2>;
+ fsl,nor-size = <0x1000000>;
+ status = "okay";
+
+ flash0: s25fl128s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl128s";
+ spi-max-frequency = <66000000>;
+ m25p,ddr-quad-read = <1>;
+ reg = <0>;
+
+ partition@0 {
+ label = "s25fl128s-0";
+ reg = <0x0 0x1000000>;
+ };
+ };
+
+ flash1: s25fl128s@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl128s";
+ spi-max-frequency = <66000000>;
+ m25p,ddr-quad-read = <1>;
+ reg = <1>;
+
+ partition@0x0 {
+ label = "s25fl128s-1";
+ reg = <0x0 0x1000000>;
+ };
+ };
+};
--
1.7.1
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