On Fri, 2013-08-16 at 16:36 -0600, Stephen Warren wrote: > On 08/14/2013 10:48 AM, dinguyen@xxxxxxxxxx wrote: > > From: Dinh Nguyen <dinguyen@xxxxxxxxxx> > > > > Add bindings for SD/MMC for SOCFPGA. > > > diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt > > > +* altr,sysmgr: Should be the phandle to the system_mgr node. As this is where > > + this where the register that controls the CIU clock phases > > + reside. > > On the surface, this binding series seems OK, but I do have a question: > how is the sysmgr phandle used? > > I assume there's some register in this syscon device that resets or > enables or otherwise controls this MSHC module. How does the code know > which register it is? The phandle in the altr,sysmgr property would > usually be followed by a/some cell(s) that encode this information, so > that the MSHC driver doesn't have to know anything about the layout of > the syscon registers, and so the sysconf driver doesn't have to know > anything about the identity of the MSHC client device. There is a #define SYSMGR_SDMMCGRP_CTRL_OFFSET that is in dw_mmc-socfpga.c. This defines the offset from the base address that the sysmgr phandle will give me. > > That way, the MSHC driver will work fine if a HW designer has dropped > the MSHC IP block into a completely different SoC with a different > syscon register layout. > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
