On Mon, Aug 19, 2013 at 03:35:58PM -0600, Stephen Warren wrote: > > + "core" The core clock of spdif controller > > + "rxtx<0-7>" Clock source list for tx and rx clock. > > + This clock list should be identical to > > + the source list connecting to the spdif > > + clock mux in "SPDIF Transceiver Clock > > + Diagram" of SoC reference manual. It > > + can also be referred to TxClk_Source > > + bit of register SPDIF_STC. > > So, the HW block has 1 clock input, yet there's a mux somewhere else in > the SoC which has 8 inputs? > > If so, I'm not completely sure it's correct to reference anything other > than the "core" clock in this binding. I think the other clocks would be > more suitably represented in the system-level "sound card" binding that > I guess patch 2/2 (which I haven't read yet) adds, since I assume those > clock are more to do with system-level clock tree setup decisions, and > might not even exist in some other SoC that included this IP block. > > What do others think, assuming I'm correct about my HW design assumptions? The core clock is being only needed when accessing registers of this IP. Thus, in the driver, I let regmap handle it. While the other 8 clocks are actual reference clocks for Tx. Tx clock needs to select one of them that can easily derive a child clock matching the tx sample rate. This is essential for the IP, so I don't think it's nicer to put into machine driver. Thank you Nicolin -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
