Hi Bhushan, I'll revise some as you suggest. Just a few replies here. On Mon, Aug 19, 2013 at 12:38:11PM +0800, Bhushan Bharat-R65777 wrote: > > We here suppose the reset bit would be cleared -- "The software reset will last > > 8 cycles." from RM, so if this happened to be a failure, the whole IP module > > won't be normally working as well. > > Also add a comment describing this against why cycle = 1000 is selected. If it is done in 8 cycles, 1000-cycle will be surely a safe value for it. As long as it finished in 8 cycles, it would quit anyway. Why against? > > > > +static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) > > > > +{ > > > > + /* Sync all registers after reset */ > > > > > > Where us sync :) ? > > > > The "return true" would do that. For volatile registers, if no "return true" > > here, the whole regmap would use the value in cache, while for some bits > > we need to trace its true value from the physical registers not from cache. > > Where will be device registers cached? Do not we program them to be non-cacheable in core? regmap has a regcache for all the mapped registers. Set the regsiters as volatile will allow the driver to sync the regcache with physical memory each time when using regmap_read/write/update_bits(). But I think I can try to use the regcache_bypass instead. Thank you, Nicolin Chen -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html