On Friday 16 August 2013, Sebastian Hesselbarth wrote:
> + cpu@0 {
> + compatible = "marvell,sheeva-v7";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <0>;
> + };
...
> + l2: l2-cache-controller@1ac0000 {
> + compatible = "marvell,aurora-outer-cache";
> + reg = <0x1ac0000 0x1000>;
> + cache-level = <2>;
> + };
> +
> + gic: interrupt-controller@1ad0000 {
> + compatible = "arm,cortex-a9-gic";
> + reg = <0x1ad1000 0x1000
> + 0x1ad0100 0x0100>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + local-timer@1ad0600 {
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0x1ad0600 0x20>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpu0clk>;
> + };
This seems like a strange combination. I would have expected either PJ4+Aurora+apbtimer
or A9+pl310+localtimer, based on what I found in the chromecast kernel source.
Do you have more information here about what is used on the two variants?
Arnd
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
