On Aug 16, 2013, at 12:19 PM, Punit Agrawal wrote:
> The CCI PMU can profile bus transactions at the master and slave
> interfaces of the CCI. The PMU can be used to observe an aggregated view
> of the bus traffic between the various components connected to the CCI.
>
> Extend the existing CCI driver to support the PMU by registering a perf
> backend for it.
>
> Document the device tree binding to describe the CCI PMU.
>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
> Cc: Nicolas Pitre <nico@xxxxxxxxxx>
> Cc: Dave Martin <dave.martin@xxxxxxxxxx>
> Cc: Rob Herring <rob.herring@xxxxxxxxxxx>
> Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
> Cc: Stephen Warren <swarren@xxxxxxxxxxxxx>
> Cc: Will Deacon <will.deacon@xxxxxxx>
> Signed-off-by: Punit Agrawal <punit.agrawal@xxxxxxx>
> ---
>
> Hi,
>
> This is the second version of the CCI PMU driver. The changes incorporate review
> comments on device tree bindings and corresponding update to the driver.
>
> Cheers,
> Punit
>
> Will, I've dropped your reviewed-by tag due to the changes. Let me know if you are
> ok with the changes and I'll add the tag.
>
> Changes since v1:
> * Dropped requirement for node name.
> * Dropped compatible strings for different revisions - rely on peripheral id
> register to provide the revision.
> * Change interrupt bindings to require overflow interrupt per counter.
>
> Documentation/devicetree/bindings/arm/cci.txt | 44 ++
> drivers/bus/arm-cci.c | 628 +++++++++++++++++++++++++
> 2 files changed, 672 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
> index 92d36e2..7cf35bc 100644
> --- a/Documentation/devicetree/bindings/arm/cci.txt
> +++ b/Documentation/devicetree/bindings/arm/cci.txt
> @@ -79,6 +79,40 @@ specific to ARM.
> corresponding interface programming
> registers.
>
> + - CCI PMU node
> +
> + Parent node must be CCI interconnect node.
> +
> + A CCI pmu node must contain the following properties:
> +
> + - compatible
> + Usage: required
> + Value type: <string>
> + Definition: must be "arm,cci-400-pmu"
> +
> + - reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: the base address and size of the
> + corresponding interface programming
> + registers.
> +
> + - interrupts:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: comma-separated list of counter overflow
> + interrupts, one per counter. The interrupts
> + must be specified starting with the cycle
> + counter overflow interrupt, followed by
> + counter0 overflow interrupt, counter1
> + overflow interrupt,..., counterN overflow
> + interrupt.
> +
> + The CCI PMU has an interrupt signal for each
> + counter. Typically, the number of
> + interrupts will be equal to the number of
> + counters.
> +
> * CCI interconnect bus masters
>
> Description: masters in the device tree connected to a CCI port
> @@ -163,6 +197,16 @@ Example:
> interface-type = "ace";
> reg = <0x5000 0x1000>;
> };
> +
> + pmu@9000 {
> + compatible = "arm,cci-400-pmu,rev0";
drop the ',rev0'
> + reg = <0x9000 0x5000>;
> + interrupts = <0 101 4>,
> + <0 102 4>,
> + <0 103 4>,
> + <0 104 4>,
> + <0 105 4>;
> + };
> };
>
> This CCI node corresponds to a CCI component whose control registers sits
[snip]
- k
--
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