On 08/15/2013 04:42 AM, Lorenzo Pieralisi wrote:
> In order to extend the current cpu nodes bindings to newer CPUs
> inclusive of AArch64 and to update support for older ARM CPUs this
> patch updates device tree documentation for the cpu nodes bindings.
>
> Main changes:
> - adds 64-bit bindings
> - define usage of #address-cells
> - defines behaviour on pre and post v7 uniprocessor systems
> - adds ARM 11MPcore specific reg property definition
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 424 ++++++++++++++++++++++---
> 1 file changed, 377 insertions(+), 47 deletions(-)
>
The binding looks mostly fine to me.
[snip]
> + "faraday,fa526"
> + "intel,sa110"
> + "intel,sa1100"
> + "marvell,feroceon"
> + "marvell,mohawk"
> + "marvell,pj4"
> + "marvell,sheeva-v7"
> + "marvell,xsc3"
> + "marvell,xscale"
Better make sure the Marvell folks are happy with these. We don't need
another rename here. I'm too annoyed with all the renames to pay attention.
> +
> +Example 4 (ARM Cortex-A57 64-bit system running OS in AArch64):
> +
Going back to my comments that the dtb can't be dependent on the OS,
these 2 examples don't make sense.
> +
> +Example 5 (ARM Cortex-A57 64-bit system running OS in AArch32):
This example should be removed.
Rob
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + };
> +
> + cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + };
> +
> + cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + };
> +};
>
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