On Wed, Aug 14, 2013 at 03:59:42PM +0300, Ivan T. Ivanov wrote: > From: "Ivan T. Ivanov" <iivanov@xxxxxxxxxx> > > These drivers handles control and configuration of the HS > and SS USB PHY transceivers. They are part of the driver > which manage Synopsys DesignWare USB3 controller stack > inside Qualcomm SoC's. > > Signed-off-by: Ivan T. Ivanov <iivanov@xxxxxxxxxx> > --- [..] > diff --git a/drivers/usb/phy/phy-msm-dwc3-hs.c b/drivers/usb/phy/phy-msm-dwc3-hs.c > new file mode 100644 > index 0000000..465a8f5 > --- /dev/null > +++ b/drivers/usb/phy/phy-msm-dwc3-hs.c [..] > + > +struct msm_dwc3_hs_phy { > + struct usb_phy phy; > + void __iomem *base; > + struct device *dev; > + > + struct clk *xo_clk; > + struct clk *sleep_a_clk; > + > + struct regulator *v3p3; > + struct regulator *v1p8; > + struct regulator *vddcx; > + struct regulator *vbus; > +}; > + > +#define phy_to_dwc3_phy(x) container_of((x), struct msm_dwc3_hs_phy, phy) > + > + > +/** > + * > + * Write register with debug info. what debug info? > + * > + * @base - DWC3 base virtual address. > + * @offset - register offset. > + * @val - value to write. > + * > + */ > +static inline void msm_dwc3_hs_write(void *base, u32 offset, u32 val) You've dropped __iomem here; have you run through sparse? > +{ > + iowrite32(val, base + offset); > +} > + > +/** > + * Write register and read back masked value to confirm it is written > + * > + * @base - DWC3 base virtual address. > + * @offset - register offset. > + * @mask - register bitmask specifying what should be updated > + * @val - value to write. > + * > + */ > +static inline void msm_dwc3_hs_write_readback(void *base, u32 offset, > + const u32 mask, u32 val) > +{ Same comment here. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html