Hi, On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote: <snip> > > > + /* > > + * DWC3 Core requires its CORE CLK (aka master / bus clk) to > > + * run at 125Mhz in SSUSB mode and >60MHZ for HSUSB mode. > > + */ > > + clk_set_rate(mdwc->core_clk, 125000000); > > if this is dwc3's core clock, why don't we teach dwc3.ko about this > requirement ? Just make sure to have it optional, since x86 and OMAP > wouldn't need direct fiddling with the clocks. I believe this is Qualcomm specific requirement. Something is modified inside DWC in respect of the clocks. I will like to keep this here, in the glue layer driver. Regards, Ivan -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
