Am Donnerstag, den 08.08.2013, 19:41 +0530 schrieb Viresh Kumar: > On 8 August 2013 19:28, Lucas Stach <l.stach@xxxxxxxxxxxxxx> wrote: > > From what I learned those voltage levels are dependent on both the > > Speedo and the process ID of the specific Tegra processor. So you really > > get a two dimensional mapping table instead of a single OPP. > > Also you can not scale the CPU voltage on it's own, but have to make > > sure the core voltage isn't too far away from. Then core voltage also > > depends on the operating states of engines like GR2D or even display. > > So if they depend on a certain type of SoC, which they should, then we > can get these initialized from that SoC's dts/dtsi file instead of a common > file.. And so that would resolve the issue you just reported. > You can certainly define the mapping table in DT where a specialized Tegra cpufreq driver could read it in and then map frequency to voltage. But that's a runtime decision, as Speedo and process ID are fuse values and can not be represented in DT. > Now I haven't proposed in the patch that we will change these voltage > levels at all.. This is regulator specific code and would come into play > only when regulators are registered for cpu.. Otherwise we will just > play with frequency.. > > Passing OPP instead of just list of frequencies is the generic way this > is done now a days.. The problem with this is that the hardware description now associates voltages with certain frequencies and even if they are not used by the Linux driver they are plain wrong. Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
