On Wednesday, July 31, 2013 5:14 PM, Jingoo Han <jg1.han@xxxxxxxxxxx> wrote: > Exynos PCIe IP consists of Synopsys specific part and Exynos > specific part. Only core block is a Synopsys designware part; > other parts are Exynos specific. > Also, the Synopsys designware part can be shared with other > platforms; thus, it can be split two parts such as Synopsys > designware part and Exynos specific part. > > Signed-off-by: Jingoo Han <jg1.han@xxxxxxxxxxx> > Cc: Pratyush Anand <pratyush.anand@xxxxxx> > Cc: Mohit KUMAR <Mohit.KUMAR@xxxxxx> Hi Bjorn Helgaas, There is no comment for last 2 weeks. Will you accept this patch? Best regards, Jingoo Han > --- > Changes since v4: > - fixed section mismatch warnings > - fixed sparse warnings > > .../devicetree/bindings/pci/designware-pcie.txt | 3 + > arch/arm/boot/dts/exynos5440.dtsi | 2 + > drivers/pci/host/Makefile | 3 +- > drivers/pci/host/pci-exynos.c | 530 ++++++++++ > drivers/pci/host/pcie-designware.c | 1011 ++++++-------------- > drivers/pci/host/pcie-designware.h | 65 ++ > 6 files changed, 874 insertions(+), 740 deletions(-) > create mode 100644 drivers/pci/host/pci-exynos.c > create mode 100644 drivers/pci/host/pcie-designware.h -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
