On Thu, Nov 28, 2024 at 10:01 AM Alireza Sanaee <alireza.sanaee@xxxxxxxxxx> wrote: > > Hi Better to send questions like this to devicetree-spec@xxxxxxxxxxxxxxx if you want them to be seen. > I was working on some scenarios where I have multi-threading on for my ARM CPUs and would like to share L1 caches between two hyperthreaded cores. This is particularly possible to be expressed via ACPI PPTT tables, and it is important to be able to express the same thing on both devicetree and ACPI PPTT because some use device tree and some use PPTT table for topology and sharing purposes on ARM. Currently L1 caches are expressed via some properties within CPU object and it seems not possible to use a separate cache object for L1 looking at the latest spec. I wonder what the thought are on this? The easiest thing to do here is that each thread within a core should be a 'reg' entry. So if you have 2 threads per core, the cpu nodes would have 2 entries in 'reg'. This is what the DT spec says. Though the spec says to do that if the MMU is shared, I would put that down as powerpc specific. As the spec came from ePAPR, there's still a lot of powerpc specifics left. (Patches welcome.) I don't think we've ever supported multi-threading with DT on ARM, so likely there might be some issues to fix in the kernel. Rob
