On Thu, Apr 21, 2022 at 12:25 PM Ramon Fried <rfried.dev@xxxxxxxxx> wrote: > > On Thu, Apr 21, 2022 at 3:55 PM Arnd Bergmann <arnd@xxxxxxxx> wrote: > > > > On Thu, Apr 21, 2022 at 12:33 PM Ramon Fried <rfried.dev@xxxxxxxxx> wrote: > > > > > > Hi all, > > > This is the second time in my career that I've stumbled upon a SOC > > > which has 32bit memory aliasing for high memory for the usage of > > > drivers that can only address 32bit address space. > > > > > > Basically, a subset of a memory higher than 4GB can be accessed also > > > through a range in the low 4GB addresses. > > > > > > I didn't see any support for this neither Linux kernel nor in device > > > tree. I'm wondering if you considered adding a way to describe such > > > addressing in the device tree, and maybe later Linux can add support > > > for it. > > > > I think we have some of those already, notably the TI Keystone platform, > > which only lists one of the two areas in the DT. > > > > It probably does not matter which one it is, but it may help to have > > at least some memory in the lower address range. > > > > In either case, make sure to add the correct dma-ranges properties to > > describe which memory is visible to which devices at a given address. > > > > Arnd > Hi Arnd. > What you suggest will of course work, and this is how I planned to implement it. > The problem, IMO, is that the addressing of the SOC it's not obvious > from the device tree. > My understanding is that device-tree should describe the hardware, it > just looks like a workaround to me. The h/w has some translation from one address to another and that's exactly what 'dma-ranges' is for. How is that not describing the h/w? Rob
