On Wed, May 15, 2019 at 12:19 PM Paul Walmsley <paul.walmsley@xxxxxxxxxx> wrote: > > Add an initial "cpus" schema, requested by Rob Herring. This is based I really just meant add a RiscV specific schema, but we should probably have a common one too. > on the Devicetree specification 0.2 at: > > https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.2 > > Much of the descriptive text comes from that document. There are a > few differences: this document is more tolerant than the > specification. For example, POWER-specific properties are not > included, since those seem better served by POWER-specific DT binding > documents, rather than a generic document. This binding also tolerates > the absence of some properties that are not required in practice, such as > the "clock-frequency" property. > > Signed-off-by: Paul Walmsley <paul.walmsley@xxxxxxxxxx> > Cc: Rob Herring <robh@xxxxxxxxxx> > --- > schemas/cpus.yaml | 279 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 279 insertions(+) > create mode 100644 schemas/cpus.yaml > > diff --git a/schemas/cpus.yaml b/schemas/cpus.yaml > new file mode 100644 > index 0000000..9b7d95d > --- /dev/null > +++ b/schemas/cpus.yaml > @@ -0,0 +1,279 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-clause > +# Copyright (C) 2018-2019 SiFive, Inc. > +# > +# Description text is from the Devicetree Specification at > +# https://www.devicetree.org/specifications/ > +# which is > +# Copyright 2008,2011 Power.org, Inc. > +# Copyright 2008,2011 Freescale Semiconductor, Inc. > +# Copyright 2008,2011 International Business Machines Corporation > +# Copyright 2016,2017 Linaro,Ltd. > +# Copyright 2016,2017 Arm,Ltd. > +# > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cpus.yaml# > +$schema: http://devicetree.org/meta-schemas/base.yaml# > + > +title: Common cpus binding > + > +maintainers: > + - Devicetree Specification Mailing List <devicetree-spec@xxxxxxxxxxxxxxx> > + > +description: |+ > + In Devicetree data files, the layout of CPUs is described in the > + "cpus" node. This node in turn contains a number of subnodes > + representing CPUs, which define properties for every cpu. > + > + Bindings for CPU nodes follow the Devicetree Specification, available from: > + > + https://www.devicetree.org/specifications/ > + > +properties: > + $nodename: > + const: cpus > + description: > + A /cpus node is required for all Devicetrees. It does not represent > + a real device in the system, but acts as a container for child "cpu" > + nodes which represent the systems' CPUs. > + > + '#address-cells': > + $ref: "/schemas/types.yaml#/definitions/uint32" No need to define the type as the core schemas already do that. > + minimum: 1 > + description: > + The value specifies how many cells each element of the reg property > + array takes in children of this node. > + > + '#size-cells': > + const: 0 > + > +patternProperties: > + '^cpu@[0-9a-f]+$': > + type: object > + properties: > + device_type: > + const: cpu > + > + reg: > + oneOf: > + - $ref: "/schemas/types.yaml#/definitions/uint32" > + - $ref: "/schemas/types.yaml#/definitions/uint32-array" uint32 is a subset of uint32-array, so it isn't needed. > + description: > + Defines a unique CPU/thread ID for the CPU/threads represented > + by the CPU node. > + > + compatible: > + $ref: "/schemas/types.yaml#/definitions/string-array" The type is already defined in the core schema. So just need 'compatible: true' here so you can have it in 'required'. > + > + clock-frequency: > + oneOf: > + - $ref: "/schemas/types.yaml#/definitions/uint32" > + - $ref: "/schemas/types.yaml#/definitions/uint64" The type is already defined in the core schema. > + description: > + Specifies the current clock speed of the CPU in Hertz. > + > + timebase-frequency: > + oneOf: > + - $ref: "/schemas/types.yaml#/definitions/uint32" > + - $ref: "/schemas/types.yaml#/definitions/uint64" > + minimum: 1 > + description: > + Specifies the current frequency at which the timebase and the > + decrementer registers are updated (in Hertz). > + > + enable-method: > + $ref: "/schemas/types.yaml#/definitions/string-array" > + description: > + Describes the method by which a CPU in a disabled state is enabled. > + This property is required for CPUs with a status property with a > + value of "disabled". The value consists of one or more strings > + that define the method to release this CPU. If a client program > + recognizes any of the methods, it may use it. > + > + cpu-release-addr: > + $ref: "/schemas/types.yaml#/definitions/uint64" > + description: > + This value specifies the physical address of a spin table entry that > + releases a secondary CPU from its spin loop. > + > + cache-op-block-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the block size in bytes upon which cache block instructions > + operate. Required if different than the L1 cache block size. > + > + reservation-granule-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the reservation granule size supported by this processor > + in bytes. > + > + mmu-type: > + type: string > + description: > + Specifies the CPU's MMU type. > + > + cache-unified: > + $ref: "/schemas/types.yaml#/definitions/flag" > + description: > + If present, specifies the cache has a unified organization. If not > + present, specifies that the cache has a Harvard architecture with > + separate caches for instructions and data. > + > + cache-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the size in bytes of a unified cache. Required if the > + cache is unified (combined instructions and data) > + > + cache-sets: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the number of associativity sets in a unified cache. > + Required if the processor has a unified cache (combined > + instructions and data) > + > + cache-block-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the block size in bytes of a unified cache. > + Required if the processor has a unified cache (combined > + instructions and data) > + > + cache-line-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the line size in bytes of a unified cache, if > + different than the cache block size. Required if the processor has > + a unified cache (combined instructions and data) > + > + i-cache-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the size in bytes of the instruction cache. Required if > + the CPU has a separate cache for instructions. > + > + i-cache-sets: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the number of associativity sets in the instruction cache. > + Required if the CPU has a separate cache for instructions. > + > + i-cache-block-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the block size in bytes of the instruction cache. > + Required if the processor has a separate cache for instructions. > + > + i-cache-line-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the line size in bytes of the instruction cache, if > + different than the cache block size. Required if the CPU has > + a separate cache for instructions. > + > + d-cache-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the size in bytes of the data cache. Required if > + the CPU has a separate cache for data. > + > + d-cache-sets: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the number of associativity sets in the data cache. > + Required if the CPU has a separate cache for data. > + > + d-cache-block-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the block size in bytes of the data cache. > + Required if the processor has a separate cache for data. > + > + d-cache-line-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + description: > + Specifies the line size in bytes of the data cache, if > + different than the cache block size. Required if the CPU has > + a separate cache for data. > + > + next-level-cache: > + $ref: "/schemas/types.yaml#/definitions/phandle" > + description: > + If present, indicates that another level of cache exists. The > + value is the phandle of the next level of cache. All these cache properties are defined already in schemas/cache.yaml. Need to expand the $node-name to 'cpu' nodes though. > + > + tlb-split: > + $ref: "/schemas/types.yaml#/definitions/flag" > + description: > + If present, specifies that the TLB has a split configuration, with > + separate TLBs for instructions and data. If absent, specifies that > + the TLB has a unified configuration. Required for a CPU with a > + TLB in a split configuration. > + > + tlb-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + minimum: 1 > + description: > + Specifies the number of entries in the TLB. Required for a CPU > + with a unified TLB for instruction and data addresses. > + > + tlb-sets: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + minimum: 1 > + description: > + Specifies the number of associativity sets in the TLB. Required for > + a CPU with a unified TLB for instruction and data addresses. > + > + d-tlb-size: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + minimum: 1 > + description: > + Specifies the number of entries in the data TLB. Required for a CPU > + with a split TLB for instruction and data addresses. > + > + d-tlb-sets: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + minimum: 1 > + description: > + Specifies the number of associativity sets in the data TLB. > + Required for a CPU with a split TLB for instruction and data > + addresses. > + > + i-tlb-size: A regex can capture all 3 variants. Though maybe that doesn't work with dependencies? > + $ref: "/schemas/types.yaml#/definitions/uint32" > + minimum: 1 > + description: > + Specifies the number of entries in the instruction TLB. Required > + for a CPU with a split TLB for instruction and data addresses. > + > + i-tlb-sets: > + $ref: "/schemas/types.yaml#/definitions/uint32" > + minimum: 1 > + description: > + Specifies the number of associativity sets in the instruction TLB. > + Required for a CPU with a split TLB for instruction and data > + addresses. > + > + required: > + - device_type > + - reg > + - compatible > + > + dependencies: > + cpu-release-addr: > + properties: > + enable-method: > + const: spin-table > + cache-size: [ 'cache-unified' ] > + cache-sets: [ 'cache-unified' ] > + cache-block-size: [ 'cache-unified' ] > + cache-line-size: [ 'cache-unified' ] > + d-tlb-size: [ 'tlb-split' ] > + d-tlb-sets: [ 'tlb-split' ] > + i-tlb-size: [ 'tlb-split' ] > + i-tlb-sets: [ 'tlb-split' ] > + > +required: > + - '#address-cells' > + - '#size-cells' > -- > 2.20.1 >
