> -----Original Message----- > From: Rafael J. Wysocki [mailto:rjw@xxxxxxxxxxxxx] > Sent: Wednesday, March 19, 2014 9:42 AM > To: Zhang Zhuoyu-B46552 > Cc: viresh.kumar@xxxxxxxxxx; cpufreq@xxxxxxxxxxxxxxx; linux- > pm@xxxxxxxxxxxxxxx; Tang Yuantian-B29983 > Subject: Re: [PATCH] cpufreq: powerpc: replace CPUFREQ_ETERNAL with > cpufreq transition latency for FSL e500mc Socs > > On Monday, March 17, 2014 01:29:28 PM Zhuoyu Zhang wrote: > > According to the data provided by HW Team, at least 12 internal > > platform clock cycles are required to stabilize a DFS clock switch on > > FSL e500mc Socs. This patch replaces the CPUFREQ_ETERNAL with > appropriate HW clock transition latency to make DFS governors work > normally on Freescale e500mc boards. > > Please sign off the patch. I can't apply it without your sign-off. Sorry to miss the "sign-off", I already sent another version for your review. --Zhuoyu > > > --- > > drivers/cpufreq/ppc-corenet-cpufreq.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c > > b/drivers/cpufreq/ppc-corenet-cpufreq.c > > index 051000f..ff7b625 100644 > > --- a/drivers/cpufreq/ppc-corenet-cpufreq.c > > +++ b/drivers/cpufreq/ppc-corenet-cpufreq.c > > @@ -21,6 +21,7 @@ > > #include <linux/of.h> > > #include <linux/slab.h> > > #include <linux/smp.h> > > +#include <sysdev/fsl_soc.h> > > > > /** > > * struct cpu_data - per CPU data struct @@ -205,7 +206,7 @@ static > > int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy) > > for_each_cpu(i, per_cpu(cpu_mask, cpu)) > > per_cpu(cpu_data, i) = data; > > > > - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; > > + policy->cpuinfo.transition_latency = (12 * NSEC_PER_SEC) / > > +fsl_get_sys_freq(); > > of_node_put(np); > > > > return 0; > > > > -- > I speak only for myself. > Rafael J. Wysocki, Intel Open Source Technology Center. > ��.n��������+%������w��{.n��������^n�r������&��z�ޗ�zf���h���~����������_��+v���)ߣ�
