On Thu, Jul 26, 2012 at 02:11:21PM +0100, Mark Brown wrote: > On Thu, Jul 19, 2012 at 11:54:41PM +0800, Shawn Guo wrote: > > > +Optional properties: > > +- transition-latency: Specify the possible maximum transition latency, > > + in unit of nanoseconds. > > This should make it clear that the transition latency being documented > here is just that for the core clock change itself, there may be other > sources of latency like the regulator ramp time or reprogramming PLLs. I think it's the total time and board dts can over-write it if it needs. Different transitions between different operating points may differ, and regulator may be able to indicate the transition time but clk don't have such api, and probably not worth to have. Thanks Richard -- To unsubscribe from this list: send the line "unsubscribe cpufreq" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
