Am Samstag 14 Januar 2012, 22:09:57 schrieb Heiko Stübner: > The S3C2416/S3C2450 SoCs support two sources for the armclk. > > The first source is the so called armdiv which divides the msysclk down > to provide necessary cpu rates. In this mode the core voltage must be > always at 1.3V. The frequency from the armdiv is not allowed to be > lower than the hclk frequency. > > In the second mode the armclk can be sourced directly from the hclk in > the so called "dynamic voltags scaling" (dvs) mode. Here the armdiv > isn't used at all. Also in this mode the core voltage may be lowered. > Existing hardware and tests with it suggest 1.0V as sufficient. > > When changing the clock source to the armdiv from the hclk, the SoC > shows stability issues if the new frequency is higher than the current > hclk frequency. Hence the driver always forces the armdiv to the hclk > frequency before the source change and lets the cpufreq issue another > set_target call for higher frequencies. > > To mark the hclk frequency as lower as the corresponding armdiv > frequency it is set 1MHz below the real frequency. This lets the cpufreq > framework change between 133MHz based on hclk and 133MHz based on armdiv > at will. > > Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx> ping? Thanks Heiko -- To unsubscribe from this list: send the line "unsubscribe cpufreq" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
