Use the regulator framework to provide optional support for DVFS in
the S3C cpufreq driver. When a software controllable regulator is
configured the driver will use it to lower the supply voltage when
running at a lower frequency, giving improved power savings.
When regulator support is disabled or no regulator can be obtained
for VDDARM the driver will fall back to scaling only the frequency.
Signed-off-by: Mark Brown <broonie@xxxxxxxxxxxxxxxxxxxxxxxxxxx>
---
arch/arm/plat-s3c/cpufreq.c | 144 ++++++++++++++++++++++++++++++++++++++-----
1 files changed, 129 insertions(+), 15 deletions(-)
diff --git a/arch/arm/plat-s3c/cpufreq.c b/arch/arm/plat-s3c/cpufreq.c
index 396866e..bc56ec5 100644
--- a/arch/arm/plat-s3c/cpufreq.c
+++ b/arch/arm/plat-s3c/cpufreq.c
@@ -15,20 +15,36 @@
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <linux/err.h>
+#include <linux/regulator/consumer.h>
static struct clk *armclk;
+static struct regulator *vddarm;
+
#ifdef CONFIG_CPU_S3C6410
+struct s3c_dvfs {
+ unsigned int vddarm_min;
+ unsigned int vddarm_max;
+};
+
+static struct s3c_dvfs s3c_dvfs_table[] = {
+ [0] = { 1000000, 1000000 },
+ [1] = { 1000000, 1050000 },
+ [2] = { 1050000, 1100000 },
+ [3] = { 1050000, 1150000 },
+ [4] = { 1250000, 1350000 },
+};
+
static struct cpufreq_frequency_table s3c_freq_table[] = {
{ 0, 66000 },
- { 1, 133000 },
- { 2, 222000 },
- { 3, 266000 },
- { 4, 333000 },
- { 5, 400000 },
- { 6, 532000 },
- { 7, 533000 },
- { 8, 667000 },
+ { 0, 133000 },
+ { 1, 222000 },
+ { 1, 266000 },
+ { 2, 333000 },
+ { 2, 400000 },
+ { 3, 532000 },
+ { 3, 533000 },
+ { 4, 667000 },
{ 0, CPUFREQ_TABLE_END },
};
#endif
@@ -56,6 +72,7 @@ static int s3c_cpufreq_set_target(struct cpufreq_policy *policy,
int ret;
unsigned int i;
struct cpufreq_freqs freqs;
+ struct s3c_dvfs *dvfs;
ret = cpufreq_frequency_table_target(policy, s3c_freq_table,
target_freq, relation, &i);
@@ -66,6 +83,7 @@ static int s3c_cpufreq_set_target(struct cpufreq_policy *policy,
freqs.old = clk_get_rate(armclk) / 1000;
freqs.new = s3c_freq_table[i].frequency;
freqs.flags = 0;
+ dvfs = &s3c_dvfs_table[s3c_freq_table[i].index];
if (freqs.old == freqs.new)
return 0;
@@ -74,24 +92,96 @@ static int s3c_cpufreq_set_target(struct cpufreq_policy *policy,
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- ret = clk_set_rate(armclk, freqs.new * 1000);
-
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+#ifdef CONFIG_REGULATOR
+ if (vddarm && freqs.new > freqs.old) {
+ ret = regulator_set_voltage(vddarm,
+ dvfs->vddarm_min,
+ dvfs->vddarm_max);
+ if (ret != 0) {
+ pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+ freqs.new, ret);
+ goto err;
+ }
+ }
+#endif
+ ret = clk_set_rate(armclk, freqs.new * 1000);
if (ret < 0) {
pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
freqs.new, ret);
- return ret;
+ goto err;
}
+#ifdef CONFIG_REGULATOR
+ if (vddarm && freqs.new < freqs.old) {
+ ret = regulator_set_voltage(vddarm,
+ dvfs->vddarm_min,
+ dvfs->vddarm_max);
+ if (ret != 0) {
+ pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+ freqs.new, ret);
+ goto err_clk;
+ }
+ }
+#endif
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
pr_debug("cpufreq: Set actual frequency %lukHz\n",
clk_get_rate(armclk) / 1000);
return 0;
+
+err_clk:
+ if (clk_set_rate(armclk, freqs.old * 1000) < 0)
+ pr_err("Failed to restore original clock rate\n");
+err:
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+ return ret;
+}
+
+#ifdef CONFIG_REGULATOR
+static void __init s3c_cpufreq_constrain_voltages(void)
+{
+ int count, v, i, found;
+ struct cpufreq_frequency_table *freq;
+ struct s3c_dvfs *dvfs;
+
+ count = regulator_count_voltages(vddarm);
+ if (count < 0) {
+ pr_err("cpufreq: Unable to check supported voltages\n");
+ return;
+ }
+
+ freq = s3c_freq_table;
+ while (freq->frequency != CPUFREQ_TABLE_END) {
+ if (freq->frequency == CPUFREQ_ENTRY_INVALID)
+ continue;
+
+ dvfs = &s3c_dvfs_table[freq->index];
+ found = 0;
+
+ for (i = 0; i < count; i++) {
+ v = regulator_list_voltage(vddarm, i);
+ if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
+ found = 1;
+ }
+
+ if (!found) {
+ pr_debug("cpufreq: %dkHz unsupported by regulator\n",
+ freq->frequency);
+ freq->frequency = CPUFREQ_ENTRY_INVALID;
+ }
+
+ freq++;
+ }
}
+#endif
static int __init s3c_cpufreq_driver_init(struct cpufreq_policy *policy)
{
+ int ret;
struct cpufreq_frequency_table *freq;
if (policy->cpu != 0)
@@ -109,17 +199,33 @@ static int __init s3c_cpufreq_driver_init(struct cpufreq_policy *policy)
return PTR_ERR(armclk);
}
- /* Check for frequencies we can generate */
+#ifdef CONFIG_REGULATOR
+ vddarm = regulator_get(NULL, "vddarm");
+ if (IS_ERR(vddarm)) {
+ ret = PTR_ERR(vddarm);
+ pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
+ pr_err("cpufreq: Only frequency scaling available\n");
+ vddarm = NULL;
+ } else {
+ s3c_cpufreq_constrain_voltages();
+ }
+#endif
+
freq = s3c_freq_table;
while (freq->frequency != CPUFREQ_TABLE_END) {
unsigned long r;
+ /* Check for frequencies we can generate */
r = clk_round_rate(armclk, freq->frequency * 1000);
r /= 1000;
-
if (r != freq->frequency)
freq->frequency = CPUFREQ_ENTRY_INVALID;
+ /* If we have no regulator then assume startup
+ * frequency is the maximum we can support. */
+ if (!vddarm && freq->frequency > s3c_cpufreq_get_speed(0))
+ freq->frequency = CPUFREQ_ENTRY_INVALID;
+
freq++;
}
@@ -129,7 +235,15 @@ static int __init s3c_cpufreq_driver_init(struct cpufreq_policy *policy)
* write plus clock reprogramming. */
policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
- return cpufreq_frequency_table_cpuinfo(policy, s3c_freq_table);
+ ret = cpufreq_frequency_table_cpuinfo(policy, s3c_freq_table);
+ if (ret != 0) {
+ pr_err("cpufreq: Failed to configure frequency table: %d\n",
+ ret);
+ regulator_put(vddarm);
+ clk_put(armclk);
+ }
+
+ return ret;
}
static struct cpufreq_driver s3c_cpufreq_driver = {
--
1.6.2.2
--
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