Re: Erasure Coding - FPGA / Hardware Acceleration

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Den fre 14 juni 2019 kl 13:58 skrev Sean Redmond <sean.redmond1@xxxxxxxxx>:
Hi Ceph-Uers,
I noticed that Soft Iron now have hardware acceleration for Erasure Coding[1], this is interesting as the CPU overhead can be a problem in addition to the extra disk I/O required for EC pools.
Does anyone know if any other work is ongoing to support generic FPGA Hardware Acceleration for EC pools, or if this is just a vendor specific feature.


Are there numbers anywhere to see how "tough" on a CPU it would be to calculate an EC code compared to "writing a sector to
a disk on a remote server and getting an ack back" ? To my very untrained eye, it seems like a very small part of the whole picture,
especially if you are meant to buy a ton of cards to do it.

--
May the most significant bit of your life be positive.
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