On Tuesday 28 June 2005 22:45, Bryan J. Smith wrote:
> > Search google for PAE52 and filter out the non technical docs (or try
> > PAE52 +athlon). Only Bryan's posts.
>
> Dude, hit _both_ AMD _and_ Intel "programmer" guides. They discuss how
> PAE52 is a 7-part addressing model for 48-bit addressing that is also
> compatible with PAE36 model.
>
> It's not only how a PAE52 OS can run PAE36 (and 32-bit) binaries, but
> also why PAE52 program's can't use PAE36 libraries or vice-versa without
> software-level translation.
>
> PAE52 is the model _well_known_ among people building x86-64 software.
>
Yes - what exactly was that page in what manual that says "PAE52" ?
> Note, AFAIK, the Athlon MP was _never_ implemented in a board that
> supported over 4GiB.
Last time you said that, there were some boards out there that did?
> Athlon 64/Opteron _uses_ EV6! EV6 is tunneled over HyperTransport!
> It's how other bus logic, including GTL on Intel platforms, is tunneled.
And the prove is where?
> People think Athlon 64/Opteron implements HyperTransport like a
> traditional MCH. Indeed, both the Apple G5 as well as HyperTransport
> between the "northbridge" and "southbridge" for Intel GTL+ processors on
> nVidia and SiS do this.
Sis uses MultiOL? Proprietary - didn't know it was just another name for
hypertransport :-) (http://www.sis.com/hyperstreaming/tech_01.htm)
> But in the Athlon 64/Opteron, the traditional "northbridge" is moved
> into the CPU. The CPU handles the EV6 logic internally, and has direct
> connections to both the DDR SDRAM channels as well as its own
> HyperTransport interconnect to other CPUs.
Dude, its the same core according to you :-)
> By your "simplification," the "narrow bus" design of HyperTransport
> would mean its _incapable_ of supporting 64-bit GTL or EV6 logic. Dude,
> you just have to dig into the design of the core to understand this.
> The info is out there man!
Incorrect - It is exactly the point why I used the work "parallel" before when
talking to buses... SATA, firewire and all the other serial buses out there
are a completely different animal - that's why I specifically used the word
"parallel" :-) Was a nice try though...
> Anyhoo, the 40-bit physical addressing limitation of Ev6 comes into play
> in x86-64 as it is currently implemented in both AMD64 _and_ EM64T.
> Intel has extended GTL to support the same limitations as EV6.
Yep - they have - so GTL is still a 32bit bus according to you right?
> I'm sure the 4th generation of both Intel x86 and AMD x86 will overcome
> this.
>
> > Sorry, but for me, that's a little weird... So many engineers in this
> > world and only one person can see the truth?
>
> Dude, get off the "truth" non-sense.
>
> PAE52 is a reality.
The concept is - not the term :-)
if a 36bit model is called PAE36... then a 40/48bit model is called... ?
> The foundations and limitations of GTL and EV6 are reality.
>
> Most people don't understand how very different the Athlon is because
> Athlon only emulates most aspects of x86/GTL, even though it does not
> use it natively.
> And Athlon 64/Opteron is an evolution of EV6 into its current, multi-
> point, EV6-addressed NUMA/HyperTransport interconnect.
Yes, its an evolution... just like the 8086 has evolved into 64bit AMD64 and
EM64T... That means there might be some legacy things (like the A20 gate)
even on modern cpus - but the design is vastly different.
Anyway, I know is overly simplyfied but please take a look at the simple block
diagram at
http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_4699_7980%5E4703,00.html
Where in this diagram is the EV6 bus? I know its not pictured, but inside
which box or between which boxes is it so I know where to search?
Thanks,
Peter.
Peter.
