On Thursday 30 June 2005 20:25, Bryan J. Smith <b.j.smith@xxxxxxxx> wrote:
> **NOTE: ?This is a recurring theme. ?You seem fixated on the assumption
> that a system that uses a single-point-of-contention design (namely the
> Intel MCH aka "northbridge") approach would _always_ be faster. ?You
> seem to lack the understanding beyond the real design contraints of a
> partial mesh interconnect on a real system interconnect (and not just
> a peripheral interconnect hacked on as a system interconnect). ?You have
> degraded most of my commentary as a "that's a chipset issue." ?You
> seem to have a very limited understanding outside of the traditional
> PC CPU-to-memory or CPU-to-I/O via a "chipset" and that's why you
> keeping missing my points on Opteron, UltraSPARC, etc...
Sorry - I guess if you run out of arguments you need to go to stuff like
this... *shrugs* When have I ever argued about that chipset design is
better? :-) Opteron is a great example that you can do it better... US-IIIi
is crippled by its cache size not the memory design...
Where did you even get the idea I am fixated on that???
Peter.
