On Tue, Sep 19, 2023 at 11:58:37AM +0800, Pu Lehui wrote: > From: Pu Lehui <pulehui@xxxxxxxxxx> > > Add necessary Zbb instructions introduced by [0] to reduce code size and > improve performance of RV64 JIT. Meanwhile, a runtime deteted helper is > added to check whether the CPU supports Zbb instructions. > > Link: https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf [0] > Suggested-by: Conor Dooley <conor@xxxxxxxxxx> Nah, you can drop this. It was just a review comment :) > Signed-off-by: Pu Lehui <pulehui@xxxxxxxxxx> > --- > arch/riscv/net/bpf_jit.h | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h > index 8e0ef4d08..4e24fb2bd 100644 > --- a/arch/riscv/net/bpf_jit.h > +++ b/arch/riscv/net/bpf_jit.h > @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) > return IS_ENABLED(CONFIG_RISCV_ISA_C); > } > > +static inline bool rvzbb_enabled(void) > +{ > + return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); This looks like it should work, thanks for changing it. Cheers, Conor.
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