Hi, There is a common theme throughout several "bsps" in the stmmac driver which all code up the same thing: for 10M, 100M and 1G, select the appropriate 2.5MHz, 25MHz, or 125MHz clock. Rather than having every BSP implement the same thing but slightly differently, let's provide a single implementation which is passed the struct clk and the speed, and have that do the speed to clock rate decode. Note: only build tested. drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +- .../ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c | 37 ++++--------- drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 27 +++------- .../net/ethernet/stmicro/stmmac/dwmac-intel-plat.c | 35 ++++--------- drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 61 ++++++---------------- .../net/ethernet/stmicro/stmmac/dwmac-starfive.c | 29 +++------- .../net/ethernet/stmicro/stmmac/stmmac_plat_lib.c | 29 ++++++++++ .../net/ethernet/stmicro/stmmac/stmmac_plat_lib.h | 8 +++ 8 files changed, 91 insertions(+), 137 deletions(-) create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_plat_lib.c create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_plat_lib.h -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
