Pu Lehui <pulehui@xxxxxxxxxxxxxxx> writes:
> From: Pu Lehui <pulehui@xxxxxxxxxx>
>
> Add support sign-extension mov instructions for RV64.
>
> Signed-off-by: Pu Lehui <pulehui@xxxxxxxxxx>
> ---
> arch/riscv/net/bpf_jit_comp64.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index fd36cb17101a..d1497182cacf 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> emit_zext_32(rd, ctx);
> break;
> }
> - emit_mv(rd, rs, ctx);
> + switch (insn->off) {
> + case 0:
> + emit_mv(rd, rs, ctx);
> + break;
> + case 8:
> + case 16:
> + emit_slli(rs, rs, 64 - insn->off, ctx);
> + emit_srai(rd, rs, 64 - insn->off, ctx);
You're clobbering the source register (rs) here, which is correct.
(Side note: Maybe it's time to add Zbb support to the JIT soon! ;-))
Björn
