From: Dave Thaler <dthaler@xxxxxxxxxxxxx> Minor changes to improve English readability. For example: * Use "must be set to zero" phrasing as typical in IETF RFCs. * Expand LSB on first use, per RFC editor requirements. * Define htole and htobe * Define PC -- V1 -> V2: addressed comments from Alexei V2 -> V3: removed changeds Alexei didn't like Signed-off-by: Dave Thaler <dthaler@xxxxxxxxxxxxx> --- Documentation/bpf/instruction-set.rst | 37 +++++++++++++++++++-------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 751e657973f..17edf268ed8 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -74,7 +74,7 @@ For example:: 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big Note that most instructions do not use all of the fields. -Unused fields shall be cleared to zero. +Unused fields must be set to zero. As discussed below in `64-bit immediate instructions`_, a 64-bit immediate instruction uses a 64-bit immediate value that is constructed as follows. @@ -103,7 +103,9 @@ instruction are reserved and shall be cleared to zero. Instruction classes ------------------- -The three LSB bits of the 'opcode' field store the instruction class: +The encoding of the 'opcode' field varies and can be determined +from the three least significant bits (LSB) of the 'opcode' field +which holds the "instruction class", as follows: ========= ===== =============================== =================================== class value description reference @@ -216,8 +218,9 @@ The byte swap instructions use an instruction class of ``BPF_ALU`` and a 4-bit The byte swap instructions operate on the destination register only and do not use a separate source register or immediate value. -The 1-bit source operand field in the opcode is used to select what byte -order the operation convert from or to: +Byte swap instructions use the 1-bit 'source' field in the 'opcode' +field as follows. Instead of indicating the source operator, it is +instead used to select what byte order the operation converts from or to: ========= ===== ================================================= source value description @@ -235,16 +238,21 @@ Examples: dst = htole16(dst) +where 'htole16()' indicates converting a 16-bit value from host byte order to little-endian byte order. + ``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 64 means:: dst = htobe64(dst) +where 'htobe64()' indicates converting a 64-bit value from host byte order to big-endian byte order. + Jump instructions ----------------- -``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for +Instruction class ``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for otherwise identical operations. -The 'code' field encodes the operation as below: + +The 4-bit 'code' field encodes the operation as below, where PC is the program counter: ======== ===== === =========================================== ========================================= code value src description notes @@ -311,7 +319,8 @@ For load and store instructions (``BPF_LD``, ``BPF_LDX``, ``BPF_ST``, and ``BPF_ mode size instruction class ============ ====== ================= -The mode modifier is one of: +mode + one of: ============= ===== ==================================== ============= mode modifier value description reference @@ -323,7 +332,8 @@ The mode modifier is one of: BPF_ATOMIC 0xc0 atomic operations `Atomic operations`_ ============= ===== ==================================== ============= -The size modifier is one of: +size + one of: ============= ===== ===================== size modifier value description @@ -334,6 +344,9 @@ The size modifier is one of: BPF_DW 0x18 double word (8 bytes) ============= ===== ===================== +instruction class + the instruction class (see `Instruction classes`_) + Regular load and store operations --------------------------------- @@ -352,7 +365,7 @@ instructions that transfer data between a register and memory. dst = *(size *) (src + offset) -Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW``. +where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW``. Atomic operations ----------------- @@ -366,7 +379,9 @@ that use the ``BPF_ATOMIC`` mode modifier as follows: * ``BPF_ATOMIC | BPF_W | BPF_STX`` for 32-bit operations * ``BPF_ATOMIC | BPF_DW | BPF_STX`` for 64-bit operations -* 8-bit and 16-bit wide atomic operations are not supported. + +Note that 8-bit (``BPF_B``) and 16-bit (``BPF_H``) wide atomic +operations are not currently supported, nor is ``BPF_ATOMIC | <size> | BPF_ST``. The 'imm' field is used to encode the actual atomic operation. Simple atomic operation use a subset of the values defined to encode @@ -390,7 +405,7 @@ BPF_XOR 0xa0 atomic xor *(u64 *)(dst + offset) += src -In addition to the simple atomic operations, there also is a modifier and +In addition to the simple atomic operations above, there also is a modifier and two complex atomic operations: =========== ================ =========================== -- 2.33.4 -- Bpf mailing list Bpf@xxxxxxxx https://www.ietf.org/mailman/listinfo/bpf
