From: Dave Thaler <dthaler@xxxxxxxxxxxxx>
Document the discussion from the email thread on the IETF bpf list,
where it was explained that the raw format varies by endianness
of the processor.
Signed-off-by: Dave Thaler <dthaler@xxxxxxxxxxxxx>
Acked-by: David Vernet <void@xxxxxxxxxxxxx>
---
V1 -> V2: rebased on top of latest master
---
Documentation/bpf/instruction-set.rst | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst
index af515de5fc3..1d473f060fa 100644
--- a/Documentation/bpf/instruction-set.rst
+++ b/Documentation/bpf/instruction-set.rst
@@ -38,8 +38,9 @@ eBPF has two instruction encodings:
* the wide instruction encoding, which appends a second 64-bit immediate (i.e.,
constant) value after the basic instruction for a total of 128 bits.
-The basic instruction encoding is as follows, where MSB and LSB mean the most significant
-bits and least significant bits, respectively:
+The basic instruction encoding looks as follows for a little-endian processor,
+where MSB and LSB mean the most significant bits and least significant bits,
+respectively:
============= ======= ======= ======= ============
32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
@@ -63,6 +64,17 @@ imm offset src_reg dst_reg opcode
**opcode**
operation to perform
+and as follows for a big-endian processor:
+
+============= ======= ==================== =============== ============
+32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
+============= ======= ==================== =============== ============
+immediate offset destination register source register opcode
+============= ======= ==================== =============== ============
+
+Multi-byte fields ('immediate' and 'offset') are similarly stored in
+the byte order of the processor.
+
Note that most instructions do not use all of the fields.
Unused fields shall be cleared to zero.
--
2.33.4
