From: Dave Thaler <dthaler@xxxxxxxxxxxxx>
Document the discussion from the email thread on the IETF bpf list,
where it was explained that the raw format varies by endianness
of the processor.
Signed-off-by: Dave Thaler <dthaler@xxxxxxxxxxxxx>
---
Documentation/bpf/instruction-set.rst | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst
index 2d3fe59bd26..3358769dc1f 100644
--- a/Documentation/bpf/instruction-set.rst
+++ b/Documentation/bpf/instruction-set.rst
@@ -33,7 +33,7 @@ eBPF has two instruction encodings:
* the wide instruction encoding, which appends a second 64-bit immediate value
(imm64) after the basic instruction for a total of 128 bits.
-The basic instruction encoding looks as follows:
+The basic instruction encoding looks as follows for a little-endian processor:
============= ======= =============== ==================== ============
32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
@@ -41,6 +41,17 @@ The basic instruction encoding looks as follows:
immediate offset source register destination register opcode
============= ======= =============== ==================== ============
+and as follows for a big-endian processor:
+
+============= ======= ==================== =============== ============
+32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
+============= ======= ==================== =============== ============
+immediate offset destination register source register opcode
+============= ======= ==================== =============== ============
+
+Multi-byte fields ('immediate' and 'offset') are similarly stored in
+the byte order of the processor.
+
Note that most instructions do not use all of the fields.
Unused fields shall be cleared to zero.
--
2.33.4
