From: Jules Maselbas <jmaselbas@xxxxxxxxx>
Add documentation for `kalray,kv3-1-core-intc` binding.
Co-developed-by: Jules Maselbas <jmaselbas@xxxxxxxxx>
Signed-off-by: Jules Maselbas <jmaselbas@xxxxxxxxx>
Signed-off-by: Yann Sionneau <ysionneau@xxxxxxxxx>
---
Notes:
V1 -> V2: new patch
.../kalray,kv3-1-apic-mailbox.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-apic-mailbox.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-apic-mailbox.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-apic-mailbox.yaml
new file mode 100644
index 000000000000..e1eb1c9fda0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-apic-mailbox.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/kalray,kv3-1-apic-mailbox#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray kv3-1 APIC-Mailbox
+
+description: |
+ Each cluster in the Coolidge SoC includes an Advanced Programmable Interrupt
+ Controller (APIC) which is split in two part:
+ - a Generic Interrupt Controller (referred as APIC-GIC)
+ - a Mailbox Controller (referred as APIC-Mailbox)
+ The APIC-Mailbox contains 128 mailboxes of 8 bytes (size of a word),
+ this hardware block is basically a 1 KB of smart memory space.
+ Each mailbox can be independently configured with a trigger condition
+ and an input mode function.
+
+ Input mode are:
+ - write
+ - bitwise OR
+ - add
+
+ Interrupts are generated on a write when the mailbox content value
+ match the configured trigger condition.
+ Available conditions are:
+ - doorbell: always raise interruption on write
+ - match: when the mailbox's value equal the configured trigger value
+ - barrier: same as match but the mailbox's value is cleared on trigger
+ - threshold: when the mailbox's value is greater than, or equal to, the
+ configured trigger value
+
+ Since this hardware block generates IRQs based on writes to some memory
+ locations, it is both an interrupt controller and an MSI controller.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ const: kalray,kv3-1-apic-mailbox
+ "#interrupt-cells":
+ const: 1
+ description:
+ The IRQ number.
+ interrupt-controller: true
+ interrupt-parent: true
+ interrupts:
+ maxItems: 128
+ description: |
+ Specifies the interrupt line(s) in the interrupt-parent controller node;
+ valid values depend on the type of parent interrupt controller
+ msi-controller: true
+
+required:
+ - compatible
+ - reg
+ - "#interrupt-cells"
+ - interrupt-controller
+ - interrupt-parent
+ - interrupts
+ - msi-controller
+
+examples:
+ - |
+ apic_mailbox: interrupt-controller@a00000 {
+ compatible = "kalray,kv3-1-apic-gic";
+ reg = <0 0xa00000 0 0x0f200>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&apic_gic>;
+ interrups = <0 1 2 3 4 5 6 7 8 9>;
+ };
+
+...
--
2.37.2
