On Tue, Oct 04, 2022 at 03:04:20AM +0200, KP Singh wrote: > On Mon, Oct 3, 2022 at 3:17 AM Jie Meng <jmeng@xxxxxx> wrote: > > > > SSE2 and hence lfence are architectural in x86-64 and no need to check > > whether they're supported in CPU. > > Why do you say this? > > The Instruction set reference does mention that: > > Exceptions: > > #UD If CPUID.01H:EDX.SSE2[bit 26] = 0 > > (undefined instruction when the CPUID.SSE2 bit is unset) > > and also that the CPUID feature flag is SSE2 Many x86 extensions predate x86-64. When they designed x86-64, AMD decided to make some mandatory (and hence architectural) and SSE2 is one of them[1]. CMOV, NOPL, PAE, NX etc. are other examples. These extensions' CPUID flags are still set. If code is to be shared between x86 and x86-64 one can still check CPUID, but bpf_jit_comp.c is compiled under x86-64 only so the check is redundant. There's an example Within kernel code too: arch/x86/lib/copy_user_64.S uses SSE (sfence) and SSE2 (movnti) instructions and doesn't check CPUID for their presence. --- [1] https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels > > > > Signed-off-by: Jie Meng <jmeng@xxxxxx> > > --- > > arch/x86/net/bpf_jit_comp.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c > > index d09c54f3d2e0..b2124521305e 100644 > > --- a/arch/x86/net/bpf_jit_comp.c > > +++ b/arch/x86/net/bpf_jit_comp.c > > @@ -1289,8 +1289,7 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image > > > > /* speculation barrier */ > > case BPF_ST | BPF_NOSPEC: > > - if (boot_cpu_has(X86_FEATURE_XMM2)) > > - EMIT_LFENCE(); > > + EMIT_LFENCE(); > > break; > > > > /* ST: *(u8*)(dst_reg + off) = imm */ > > -- > > 2.30.2 > >
