On 1/28/22 2:16 AM, Mark Rutland wrote:
On Fri, Jan 21, 2022 at 09:56:32PM +0800, Hou Tao wrote:Atomics for eBPF patch series adds support for atomic[64]_fetch_add, atomic[64]_[fetch_]{and,or,xor} and atomic[64]_{xchg|cmpxchg}, but it only add support for x86-64, so support these atomic operations for arm64 as well.What ordering semantics are the BPF atomics supposed to have? e.g. are those meant to be sequentially consistent, entirely relaxed, or somewhere imbetween?
The ordering semantics follows linux kernel memory model. Please see interpreter implementation at kernel/bpf/core.c. The kernel atomic_*() functions are used to implement these functions.
Basically the implementation procedure is almost mechanical translation of code snippets in atomic_ll_sc.h & atomic_lse.h & cmpxchg.h located under arch/arm64/include/asm. An extra temporary register is needed for (BPF_ADD | BPF_FETCH) to save the value of src register, instead of adding TMP_REG_4 just use BPF_REG_AX instead. For cpus_have_cap(ARM64_HAS_LSE_ATOMICS) case and no-LSE-ATOMICS case, both ./test_verifier and "./test_progs -t atomic" are exercised and passed correspondingly. Signed-off-by: Hou Tao <houtao1@xxxxxxxxxx> --- arch/arm64/include/asm/insn.h | 45 +++++-- arch/arm64/lib/insn.c | 155 +++++++++++++++++++++---
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