On Wed, Mar 31, 2021 at 5:28 PM Will Deacon <will@xxxxxxxxxx> wrote: > > On Wed, Mar 31, 2021 at 05:22:18PM +0800, Jianlin Lv wrote: > > On Tue, Mar 30, 2021 at 5:31 PM Will Deacon <will@xxxxxxxxxx> wrote: > > > > > > On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote: > > > > A64_MOV is currently mapped to Add Instruction. Architecturally MOV > > > > (register) is an alias of ORR (shifted register) and MOV (to or from SP) > > > > is an alias of ADD (immediate). > > > > This patch redefines A64_MOV and uses existing functionality > > > > aarch64_insn_gen_move_reg() in insn.c to encode MOV (register) instruction. > > > > For moving between register and stack pointer, rename macro to A64_MOV_SP. > > > > > > What does this gain us? There's no requirement for a BPF "MOV" to match an > > > arm64 architectural "MOV", so what's the up-side of aligning them like this? > > > > According to the description in the Arm Software Optimization Guide, > > Arithmetic(basic) and Logical(basic) instructions have the same > > Exec Latency and Execution Throughput. > > This change did not bring about a performance improvement. > > The original intention was to make the instruction map more 'natively'. > > I think we should leave the code as-is, then. Having a separate MOV_SP > macro s confusing and, worse, I worry that somebody passing A64_SP to > A64_MOV will end up using the zero register. > > Will OK, your concerns are justified. I have made such mistakes. Jianlin
