On Wed, 16 Dec 2020 at 08:08, Yonghong Song <yhs@xxxxxx> wrote: > > > > On 12/15/20 4:18 AM, Brendan Jackman wrote: > > Document new atomic instructions. > > > > Signed-off-by: Brendan Jackman <jackmanb@xxxxxxxxxx> > > Ack with minor comments below. > > Acked-by: Yonghong Song <yhs@xxxxxx> > > > --- > > Documentation/networking/filter.rst | 26 ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/Documentation/networking/filter.rst b/Documentation/networking/filter.rst > > index 1583d59d806d..26d508a5e038 100644 > > --- a/Documentation/networking/filter.rst > > +++ b/Documentation/networking/filter.rst > > @@ -1053,6 +1053,32 @@ encoding. > > .imm = BPF_ADD, .code = BPF_ATOMIC | BPF_W | BPF_STX: lock xadd *(u32 *)(dst_reg + off16) += src_reg > > .imm = BPF_ADD, .code = BPF_ATOMIC | BPF_DW | BPF_STX: lock xadd *(u64 *)(dst_reg + off16) += src_reg > > > > +The basic atomic operations supported (from architecture v4 onwards) are: > > Remove "(from architecture v4 onwards)". Oops, thanks. > > + > > + BPF_ADD > > + BPF_AND > > + BPF_OR > > + BPF_XOR > > + > > +Each having equivalent semantics with the ``BPF_ADD`` example, that is: the > > +memory location addresed by ``dst_reg + off`` is atomically modified, with > > +``src_reg`` as the other operand. If the ``BPF_FETCH`` flag is set in the > > +immediate, then these operations also overwrite ``src_reg`` with the > > +value that was in memory before it was modified. > > + > > +The more special operations are: > > + > > + BPF_XCHG > > + > > +This atomically exchanges ``src_reg`` with the value addressed by ``dst_reg + > > +off``. > > + > > + BPF_CMPXCHG > > + > > +This atomically compares the value addressed by ``dst_reg + off`` with > > +``R0``. If they match it is replaced with ``src_reg``, The value that was there > > +before is loaded back to ``R0``. > > + > > Note that 1 and 2 byte atomic operations are not supported. > > Adding something like below. > > Except xadd for legacy reason, all other 4 byte atomic operations > require alu32 mode. > The alu32 mode can be enabled with clang flags "-Xclang -target-feature > -Xclang +alu32" or "-mcpu=v3". The cpu version 3 has alu32 mode on by > default. Thanks, I've written it as: Except ``BPF_ADD`` _without_ ``BPF_FETCH`` (for legacy reasons), all 4 byte atomic operations require alu32 mode. Clang enables this mode by default in architecture v3 (``-mcpu=v3``). For older versions it can be enabled with ``-Xclang -target-feature -Xclang +alu32``. > > > > You may encounter BPF_XADD - this is a legacy name for BPF_ATOMIC, referring to > >
