On Fri, Nov 27, 2020 at 09:39:10PM -0800, Yonghong Song wrote: > > > On 11/27/20 9:57 AM, Brendan Jackman wrote: > > This adds instructions for > > > > atomic[64]_[fetch_]and > > atomic[64]_[fetch_]or > > atomic[64]_[fetch_]xor > > > > All these operations are isomorphic enough to implement with the same > > verifier, interpreter, and x86 JIT code, hence being a single commit. > > > > The main interesting thing here is that x86 doesn't directly support > > the fetch_ version these operations, so we need to generate a CMPXCHG > > loop in the JIT. This requires the use of two temporary registers, > > IIUC it's safe to use BPF_REG_AX and x86's AUX_REG for this purpose. > > similar to previous xsub (atomic[64]_sub), should we implement > xand, xor, xxor in llvm? yes. please. Unlike atomic_fetch_sub that can be handled by llvm. atomic_fetch_or/xor/and has to be seen as separate instructions because JITs will translate them as loop.
