On Wed, 2024-07-03 at 11:27 +0000, Puranjay Mohan wrote:
[...]
> > > > > @@ -16030,7 +16030,14 @@ static u8 get_helper_reg_mask(const struct bpf_func_proto *fn)
> > > > > */
> > > > > static bool verifier_inlines_helper_call(struct bpf_verifier_env *env, s32 imm)
> > > > > {
> > > > > - return false;
> > > > > + switch (imm) {
> > > > > +#ifdef CONFIG_X86_64
> > > > > + case BPF_FUNC_get_smp_processor_id:
> > > > > + return env->prog->jit_requested && bpf_jit_supports_percpu_insn();
> > > > > +#endif
> > > >
> > > > please see bpf_jit_inlines_helper_call(), arm64 and risc-v inline it
> > > > in JIT, so we need to validate they don't assume any of R1-R5 register
> > > > to be a scratch register
>
> They don't assume any register to be scratch (except R0) so we can
> enable this on arm64 and riscv.
Puranjay, just out of curiosity and tangential to this patch-set,
I see that get_smp_processor_id is implemented as follows in riscv jit:
emit_ld(bpf_to_rv_reg(BPF_REG_0, ctx), offsetof(struct thread_info, cpu),
RV_REG_TP, ctx);
Where bpf_to_rv_reg() refers to regmap, which in turn has the following line:
static const int regmap[] = {
[BPF_REG_0] = RV_REG_A5,
...
}
At the same time, [1] says:
> 18.2 RVG Calling Convention
> ...
> Values are returned from functions in integer registers a0 and a1 and
> floating-point registers fa0 and fa1.
[1] https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf
So, I would expect r0 to be mapped to a0, do you happen to know why is it a5?
[...]
