On Sat, May 11, 2024 at 10:34:36AM GMT, Xiao Wang wrote:
> The Zba extension provides add.uw insn which can be used to implement
> zext.w with rs2 set as ZERO.
>
> Signed-off-by: Xiao Wang <xiao.w.wang@xxxxxxxxx>
> ---
> v2:
> * Add Zba description in the Kconfig. (Lehui)
> * Reword the Kconfig help message to make it clearer. (Conor)
> ---
> arch/riscv/Kconfig | 22 ++++++++++++++++++++++
> arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> 2 files changed, 40 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 6bec1bce6586..e262a8668b41 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> preemption. Enabling this config will result in higher memory
> consumption due to the allocation of per-task's kernel Vector context.
>
> +config TOOLCHAIN_HAS_ZBA
> + bool
> + default y
> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> + depends on AS_HAS_OPTION_ARCH
> +
> config TOOLCHAIN_HAS_ZBB
> bool
> default y
> @@ -601,6 +609,20 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> depends on AS_HAS_OPTION_ARCH
>
> +config RISCV_ISA_ZBA
> + bool "Zba extension support for bit manipulation instructions"
> + depends on TOOLCHAIN_HAS_ZBA
We handcraft the instruction, so why do we need toolchain support?
> + depends on RISCV_ALTERNATIVE
Also, while riscv_has_extension_likely() will be accelerated with
RISCV_ALTERNATIVE, it's not required.
> + default y
> + help
> + Add support for enabling optimisations in the kernel when the Zba
> + extension is detected at boot.
> +
> + The Zba extension provides instructions to accelerate the generation
> + of addresses that index into arrays of basic data types.
> +
> + If you don't know what to do here, say Y.
> +
> config RISCV_ISA_ZBB
> bool "Zbb extension support for bit manipulation instructions"
> depends on TOOLCHAIN_HAS_ZBB
> diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> index f4b6b3b9edda..18a7885ba95e 100644
> --- a/arch/riscv/net/bpf_jit.h
> +++ b/arch/riscv/net/bpf_jit.h
> @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
> return IS_ENABLED(CONFIG_RISCV_ISA_C);
> }
>
> +static inline bool rvzba_enabled(void)
> +{
> + return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
> +}
> +
> static inline bool rvzbb_enabled(void)
> {
> return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
> @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
> return rv_css_insn(0x7, imm, rs2, 0x2);
> }
>
> +/* RV64-only ZBA instructions. */
> +
> +static inline u32 rvzba_zextw(u8 rd, u8 rs1)
> +{
> + /* add.uw rd, rs1, ZERO */
> + return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
> +}
> +
> #endif /* __riscv_xlen == 64 */
>
> /* Helper functions that emit RVC instructions when possible. */
> @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
>
> static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
> {
> + if (rvzba_enabled()) {
> + emit(rvzba_zextw(rd, rs), ctx);
> + return;
> + }
> +
> emit_slli(rd, rs, 32, ctx);
> emit_srli(rd, rd, 32, ctx);
> }
> --
> 2.25.1
>
Thanks,
drew
