> > I have already started implementing this on ARM64, > > Pu, can you do it for RISC-V? If you don't have cycles then I could do it after > finishing ARM64. I ended up doing it for both ARM64 and RISC-V. But I don't see as high performance improvement as we see in x86. Maybe, I missed something. Please see: ARM64: https://lore.kernel.org/bpf/20240405091707.66675-1-puranjay12@xxxxxxxxx/ RISC-V: https://lore.kernel.org/bpf/20240405124348.27644-1-puranjay12@xxxxxxxxx/ Thanks, Puranjay
