On 2024/3/24 0:49, Puranjay Mohan wrote:
Pu Lehui <pulehui@xxxxxxxxxx> writes:
On 2024/3/23 23:46, Puranjay Mohan wrote:
LLVM generates bpf_addr_space_cast instruction while translating
[snip]
/* Convert from ninsns to bytes. */
diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index f51b832eafb6..3c389e75cb96 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -1083,6 +1083,16 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
/* dst = src */
case BPF_ALU | BPF_MOV | BPF_X:
case BPF_ALU64 | BPF_MOV | BPF_X:
+ if (BPF_CLASS(insn->code) == BPF_ALU64 && insn->off == BPF_ADDR_SPACE_CAST &&
+ insn->imm == 1U << 16) {
+ emit_mv(RV_REG_T1, rs, ctx); > + emit_zextw(RV_REG_T1, RV_REG_T1, ctx);
combine mv and zextw will be better
Do you suggest doing:
emit_zextw(RV_REG_T1, rs, ctx);
Will do it in next version.
+ emit_imm(rd, (ctx->user_vm_start >> 32) << 32, ctx);
+ emit(rv_beq(RV_REG_T1, RV_REG_ZERO, 4), ctx);
+ emit_or(RV_REG_T1, rd, RV_REG_T1, ctx);
+ emit_mv(rd, RV_REG_T1, ctx);
ditto, but for or and mv
How would we combine or and mv?
also, we have a beq above and in one case both or and mv should happen,
but in other case only mv should happen.
Okay, another branch is that t1 is zero, but not rd.
Thanks,
Puranjay
