Pu Lehui <pulehui@xxxxxxxxxxxxxxx> writes: > From: Pu Lehui <pulehui@xxxxxxxxxx> > > Add necessary Zbb instructions introduced by [0] to reduce code size and > improve performance of RV64 JIT. Meanwhile, a runtime deteted helper is > added to check whether the CPU supports Zbb instructions. > > Link: https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf [0] > Signed-off-by: Pu Lehui <pulehui@xxxxxxxxxx> > --- > arch/riscv/net/bpf_jit.h | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h > index e30501b46f8f..51f6d214086f 100644 > --- a/arch/riscv/net/bpf_jit.h > +++ b/arch/riscv/net/bpf_jit.h > @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) > return IS_ENABLED(CONFIG_RISCV_ISA_C); > } > > +static inline bool rvzbb_enabled(void) > +{ > + return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); Hmm, I'm thinking about the IS_ENABLED(CONFIG_RISCV_ISA_ZBB) semantics for a kernel JIT compiler. IS_ENABLED(CONFIG_RISCV_ISA_ZBB) affects the kernel compiler flags. Should it be enough to just have the run-time check? Should a kernel built w/o Zbb be able to emit Zbb from the JIT? Björn
